Semiconductor package including fine redistribution patterns
US11923309B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2021 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Sep 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.