Double cross-couple for two-row flip-flop using CFET
US11923364B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2021 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Mar 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a cell array having tracks and rows formed on a substrate. The tracks extend perpendicularly to the rows. A logic cell is formed across two adjacent rows within the cell array. The logic cell includes a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows. Each XC includes two cross-coupled complementary field-effect-transistors. Each poly track is configured to function as an inter-row gate for the XCs. A pair of signal tracks is positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.