Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication
US11929320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2022 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Mar 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2007
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.