Sideways vias in isolation areas to contact interior layers in stacked devices

US11942416B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ehren Mannebach · Beaverton, US
• Aaron D. Lilak · Beaverton, US
• Hui Jae Yoo · Hillsboro, US
• Patrick Morrow · Portland, US
• Anh Phan · Beaverton, US
• Willy Rachmady · Beaverton, US
• Cheng-Ying Huang
• Gilbert Dewey · Beaverton, US
• Rishabh Mehandru · Portland, US

Key dates

• Filing date: Jun 28, 2019
• Grant date: Mar 26, 2024
• Expiry date: Jan 29, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.