Memory cell group read with compensation for different programming speeds
US11955184B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Aug 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.