Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
US11955424B2 · kind B2 · utility
0Cited by
18References
20Claims
0Family size
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Key dates
| Filing date | Jan 5, 2023 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Jan 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1047
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.