Patent · US Active

Data processing engine arrangement in a device

US11972132B2 · kind B2 · utility

0Cited by

43References

19Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Juan J. Noguera Serra · San Jose, US
Goran H K Bilski · Mölndal, SE
Jan Langer · Chemnitz, DE
Baris Ozgul · Dublin, IE
Richard L. Walke · Edinburgh, GB
Ralph D. Wittig · Menlo Park, US
Kornelis A. Vissers · Sunnyvale, US
Tim Tuan · San Jose, US
David Clarke · Dublin, IE

Key dates

Filing date	Dec 22, 2022
Grant date	Apr 30, 2024
Priority date	—
Expiry date	Dec 22, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/7807
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.