Package on active silicon semiconductor packages
US11978727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2017 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Sep 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1094
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.