Chamfer-less via integration scheme
US11987876B2 · kind B2 · utility
3Cited by
48References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2019 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Aug 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.