Semiconductor packages having first and second redistribution patterns
US11996358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2021 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Aug 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.