Leave-behind protective layer having secondary purpose

US11996408B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Anh Phan · Beaverton, US
• Ehren Mannebach · Beaverton, US
• Cheng-Ying Huang
• Stephanie A. Bojarski · Beaverton, US
• Gilbert Dewey · Beaverton, US
• Orb Acton · Portland, US
• Willy Rachmady · Beaverton, US

Key dates

• Filing date: Apr 21, 2022
• Grant date: May 28, 2024
• Expiry date: Aug 19, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/08
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.