Stacked forksheet transistors

US11996411B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Cheng-Ying Huang
• Gilbert Dewey · Beaverton, US
• Anh Phan · Beaverton, US
• Nicole K. Thomas · Portland, US
• Urusa Alaan · Hillsboro, US
• Seung Hoon Sung · Beaverton, US
• Christopher M. Neumann · Portland, US
• Willy Rachmady · Beaverton, US
• Patrick Morrow · Portland, US
• Hui Jae Yoo · Hillsboro, US
• Richard E. Schenker · Portland, US
• Marko Radosavljevic · Portland, US
• Jack T. Kavalieros · Portland, US
• Ehren Mannebach · Beaverton, US

Key dates

• Filing date: Jun 26, 2020
• Grant date: May 28, 2024
• Expiry date: Sep 29, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.