Inter-level handshake for dense 3D logic integration
US12002862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2021 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Apr 16, 2042 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.