Chip package, method of forming a chip package and method of forming an electrical contact
US12033972B2 · kind B2 · utility
0Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2020 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Mar 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.