Patent · US Active

Verifying the correctness of a leading zero counter

US12056465B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Michael Klein · Schenefeld, DE
Petra Leber · Ehningen, DE
Cedric Lichtenau · Stuttgart, DE
Stefan Payer · Stuttgart, DE
Kerstin Claudia Schelm · Stuttgart, DE

Key dates

Filing date	Mar 25, 2022
Grant date	Aug 6, 2024
Priority date	—
Expiry date	Apr 9, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/74
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Verifying the correctness of a leading zero counter, including: generating, based on an input value comprising a plurality of digits, a first bit vector, wherein each entry of the first bit vector indicates whether a corresponding digit of the input value is equal to zero; calculating, based on the first bit vector, a leading zero count for the input value; generating a bit mask comprising a number of leading ones equal to the leading zero count; generating a second bit vector comprising a one at a same index as a first occurring zero in the bit mask; and verifying the leading zero count based on the first bit vector and one or more of the bit mask and the second bit vector.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.