Memory apparatus and method of operation using state dependent strobe tier scan to reduce peak ICC
US12057175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Oct 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.