Load multiple primitives per thread in a graphics pipeline
US12062126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2021 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Sep 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for loading multiple primitives per thread in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with a geometry engine, shader processor input (SPI), and a plurality of compute units. The geometry engine generates primitives which are accumulated by the SPI into primitive groups. While accumulating primitives, the SPI tracks the number of vertices and primitives per group. The SPI determines wavefront boundaries based on mapping a single vertex to each thread of the wavefront while allowing more than one primitive per thread. The SPI launches wavefronts with one vertex per thread and potentially multiple primitives per thread. The compute units execute a vertex phase and a multi-cycle primitive phase for wavefronts with multiple primitives per thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.