Interconnect techniques for electrically connecting source/drain regions of stacked transistors

US12107085B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Gilbert Dewey · Beaverton, US
• Cheng-Ying Huang
• Christopher J. Jezewski · Portland, US
• Ehren Mannebach · Beaverton, US
• Rishabh Mehandru · Portland, US
• Patrick Morrow · Portland, US
• Anand S. Murthy · Beaverton, US
• Anh Phan · Beaverton, US
• Willy Rachmady · Beaverton, US

Key dates

• Filing date: Jul 7, 2023
• Grant date: Oct 1, 2024
• Expiry date: Jul 7, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.