High speed multi-level cell (MLC) programming in non-volatile memory structures
US12112800B2 · kind B2 · utility
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Key dates
| Filing date | May 26, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Sep 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.