Low power multi-level cell (MLC) programming in non-volatile memory structures
US12142315B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | May 26, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Nov 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.