Stacked source-drain-gate connection and process for forming such
US12148806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2024 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Jan 9, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.