Merged branch target buffer entries
US12153927B2 · kind B2 · utility
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2References
27Claims
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Key dates
| Filing date | Jun 1, 2020 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Jun 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Merging branch target buffer entries includes maintaining, in a branch target buffer, an entry corresponding to first branch instruction, where the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction; and accessing, based on the first branch instruction, the entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.