Semiconductor device including bonding pad metal layer structure

US12183696B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Evelyn Napetschnig · Diex, AT
• Jens Brandenburg · Munich, DE
• Christoffer Erbert · Duel, AT
• Joachim Hirschler · Villach, AT
• Oliver Humbel · Maria Elend, AT
• Thomas Rupp · Stormville, US
• Carsten Schaeffer · Annenheim, AT
• Julia Zischang · Villach, AT

Key dates

• Filing date: Aug 18, 2023
• Grant date: Dec 31, 2024
• Expiry date: Aug 18, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/13091
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.