Multi-channel transistor
US12183814B1 · kind B1 · utility
0Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Mar 25, 2024 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Mar 25, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/411
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.