Through array contact structure of three-dimensional memory device
US12185550B2 · kind B2 · utility
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14References
20Claims
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Key dates
| Filing date | Aug 8, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Aug 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) memory device includes a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack. The first stack includes first and second dielectric layers arranged alternately in a vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes an unclosed shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.