Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell
US12190946B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Aug 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.