Selective ILD deposition for fully aligned via with airgap
US12218003B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 25, 2023 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Apr 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76826
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.