Wiring in diffusion breaks in an integrated circuit
US12218135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2022 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Feb 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.