Interdigitated device stack

US12224281B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Lars Liebmann · Poughquag, US
• Jeffrey Smith · Clifton Park, US
• Daniel Chanemougame · Niskayuna, US
• Paul Gutwin · Williston, US
• Brian Tracy Cline · Austin, US
• Xiaoqing Xu · Austin, US
• David Victor Pietromonaco · San Jose, US

Key dates

• Filing date: Dec 3, 2021
• Grant date: Feb 11, 2025
• Expiry date: Jul 14, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0172
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.