Stacked transistors with different channel widths
US12230544B2 · kind B2 · utility
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21References
19Claims
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Key dates
| Filing date | Nov 2, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Nov 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.