Low power read method and a memory device capable thereof
US12243593B2 · kind B2 · utility
0Cited by
5References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 3, 2022 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Jan 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.