Dense via pitch interconnect to increase wiring density
US12266598B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Oct 24, 2022 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | May 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0284
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.