Decoupling capacitors and methods of fabrication

US12310001B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Juan G. Alzate-Vinasco · Tigard, US
• Travis W. Lajoie · Forest Grove, US
• Wilfred Gomes · Portland, US
• Fatih Hamzaoglu · Portland, US
• Pulkit Jain · Hillsboro, US
• James Waldemer · Hillsboro, US
• Mark Armstrong · Portland, US
• Bernhard Sell · Dresden, DE
• Pei-Hua Wang · Beaverton, US
• Chieh-Jen Ku · Hillsboro, US

Key dates

• Filing date: Jun 25, 2021
• Grant date: May 20, 2025
• Expiry date: Jul 7, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6728
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.