Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

US12310044B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Rishabh Mehandru · Portland, US
• Patrick Morrow · Portland, US
• Ranjith Kumar · Beaverton, US
• Cory E. Weber · Portland, US
• Seiyon Kim · Portland, US
• Stephen M. Cea · Hillsboro, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Oct 31, 2022
• Grant date: May 20, 2025
• Expiry date: Aug 2, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/473

Abstract

Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.