CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor
US12310090B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Jan 6, 2023 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Jan 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.