Bonded assembly including interconnect-level bonding pads and methods of forming the same
US12347804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2021 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Dec 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.