Stacked transistor layout for improved cell height scaling

US12363965B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ruilong Xie · Niskayuna, US
• Nicholas Anthony Lanzillo · Wynantskill, US
• Albert M. Chu · Nashua, US
• Daniel James Dechene · Watervliet, US
• Eric Miller · Watervliet, US
• Lawrence A. Clevenger · Saratoga Springs, US

Key dates

• Filing date: Aug 11, 2022
• Grant date: Jul 15, 2025
• Expiry date: Jan 26, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Embodiments of the invention include a first source region and a first drain region forming a first L-shaped layout. The first source and drain regions are formed on a bottom gate spacer material. Embodiments include a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate. One of the first source and drain regions extends in a direction beyond the bottom gate spacer material to form the first L-shaped layout, wherein the direction is parallel to a lengthwise direction of the gate.