Integrated circuit structures having cut metal gates with dielectric spacer fill

US12382721B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Leonard P. GULER · Hillsboro, US
• Chanaka D. Munasinghe · Hillsboro, US
• Makram ABD EL QADER · Hillsboro, US
• Marie T. Conte · Hillsboro, US
• Saurabh Morarka · Hillsboro, US
• Elliot N. Tan · Portland, US
• Krishna Kumar Ganesan · Hillsboro, US
• Mohit K. HARAN · Hillsboro, US
• Charles H. Wallace · Portland, US
• Tahir Ghani · Portland, US
• Sean PURSEL · Hillsboro, US

Key dates

• Filing date: Jun 15, 2021
• Grant date: Aug 5, 2025
• Expiry date: Dec 7, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0149
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.