Ultra-thin, hyper-density semiconductor packages

US12406914B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Debendra Mallik · Chandler, US
• Robert L. Sankman · Phoenix, US
• Robert M. Nickerson · Chandler, US
• Mitul Modi · Phoenix, US
• Sanka Ganesan · Chandler, US
• Rajasekaran Swaminathan · Chandler, US
• Omkar G. Karhade · Chandler, US
• Shawna M. Liff · Scottsdale, US
• Amruthavalli Pallavi Alur · Tempe, US
• Sri Chaitra Jyotsna Chavali · Chandler, US

Key dates

• Filing date: Dec 30, 2022
• Grant date: Sep 2, 2025
• Expiry date: Jul 7, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/18161
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.