Field effect transistor with backside source/drain

US12419079B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ruilong Xie · Niskayuna, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Brent A. Anderson · Jericho, US
• Kisik Choi · Hopewell Junction, US
• Su Chen Fan · Cohoes, US
• Shogo Mochizuki · Clifton Park, US
• Son Nguyen · Richland, US

Key dates

• Filing date: Oct 4, 2022
• Grant date: Sep 16, 2025
• Expiry date: Feb 8, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.