Capacitor connections in dielectric layers

US12426247B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Travis W. Lajoie · Forest Grove, US
• Abhishek A. Sharma · Hillsboro, US
• Van H. Le · Portland, US
• Chieh-Jen Ku · Hillsboro, US
• Pei-Hua Wang · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Bernhard Sell · Dresden, DE
• Tahir Ghani · Portland, US
• Gregory George · Beaverton, US
• Akash Garg · Portland, US
• Allen B. Gardiner · Portland, US
• Shem Ogadhoh · Beaverton, US
• Juan G. Alzate Vinasco · Tigard, US
• Umut Arslan · Hillsboro, US
• Fatih Hamzaoglu · Portland, US
• Nikhil MEHTA · Portland, US
• Jared Stoeger · Portland, US
• Yu-Wen Huang · Beaverton, US
• Shu Zhou · Portland, US

Key dates

• Filing date: Oct 17, 2023
• Grant date: Sep 23, 2025
• Expiry date: Oct 17, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/85

Abstract

Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.