Memory program-verify with adaptive sense time based on row location
US12431203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Mar 28, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.