Semiconductor memory device having stacked capacitor cells
US5140389A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1990 |
| Grant date | Aug 18, 1992 |
| Priority date | — |
| Expiry date | Feb 5, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.