Non-volatile semiconductor memory device with voltage stabilizing electrode
US5179427A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1992 |
| Grant date | Jan 12, 1993 |
| Priority date | — |
| Expiry date | Apr 15, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.