Staged-vacuum wafer processing system and method
US5186718A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1991 |
| Grant date | Feb 16, 1993 |
| Priority date | — |
| Expiry date | Apr 15, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/169
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processing system for workpieces such as semiconductor wafers is disclosed which incorporates multiple, isolated vacuum stages between the cassette load lock station and the main vacuum processing chambers. A vacuum gradient is applied between the cassette load lock and the main processing chambers to facilitate the use of a very high degree of vacuum in the processing chambers without lengthy pump down times. Separate robot chambers are associated with the vacuum processing chambers and the load lock(s). In addition, separate transport paths are provided between the two robot chambers to facilitate loading and unloading of workpieces. Pre-treatment and post-treatment chambers may be incorporated in the two transport paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.