Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode
US5355330A · kind A · utility
111Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1992 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Aug 19, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device whose data hold condition is not affected due to degradation of transistor characteristics by minimizing leakage charges and the switching transistor size. The semiconductor memory device employs memory cell charge holding electrode that is insulated from the remaining memory cell structure, particularly the switching transistor source drain leakage path. The write element controls the tunneling of charge carriers through such insulator to the charge holding portion or capacitor electrode, for writing data. Particularly, the write element includes a PN junction for various advantages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.