Adjustable threshold voltage conversion circuit
US5521867A · kind A · utility
20Cited by
4References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1993 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Dec 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash EPROM circuit for providing a tight erase threshold voltage distribution. The circuit includes an array of memory cells having gates, sources and drains. Bit lines are coupled to the drains of a column of cells in the memory array. A plurality of word lines are each coupled to the gates of a row of cells in the memory array. A first voltage source is coupled to the bit lines to converge threshold voltages of erased memory cells. A second voltage source is coupled to the word lines to control the threshold voltages of the erased memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.