Multistepped threshold convergence for a flash memory array
US5576991A · kind A · utility
15Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1994 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Jul 1, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of converging threshold voltages of memory cells in a flash EEPROM array after the memory cells have been erased, the method including applying a gate voltage having an initial negative value which is increased to a more positive value in steps during application of a drain disturb voltage. By applying a gate voltage with an initial negative value, leakage current during convergence is reduced enabling all cells on bit lines of the array to be converged in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.