Reduced column leakage during programming for a flash memory array
US5579261A · kind A · utility
11Cited by
4References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 21, 1995 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Apr 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programing a cell in an array of flash memory cells connected to a bit line using hot-electron injection. In the method, a negative word line voltage is applied to unselected cells connected to the bit line to create a negative gate to source voltage in the unselected cells. The negative gate to source voltage in the unselected cells is provided to prevent overerased cells, or cells which have a negative threshold, from turning on to reduce bit line leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.