Semiconductor memory device having stacked capacitors
US5583358A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 1994 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Oct 17, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.